Apparatus and method for monotonic digital calibration of a pipeline analog-to-digital converter

ABSTRACT

A method and circuit for performing a monotonic digital calibration of a pipeline analog-to-digital (A/D) converter calibrates each stage of the pipeline A/D converter while using the actual input A/D converter of the stage then being calibrated. The digital output from the stage is converted to an analog signal (e.g., integrated) and fed back for use as the analog input to the stage. This ensures that the digital output from the stage has a symmetrical waveform and that the analog input voltage to the stage remains at the input threshold level. The remaining downstream pipeline A/D converter stages are then used to measure the levels of the binary residue voltage corresponding to the two states of the binary stage output so that appropriate calibration data can be generated and stored for use in calibrating that stage. By repeating this process for each successive upstream pipeline A/D converter stage the entire pipeline A/D converter can be calibrated to help ensure the monotonicity of its A/D conversion.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to pipeline analog-to-digital (A/D)converters, and in particular, to digital calibration techniques forsuch converters.

2. Description of the Related Art

Referring to FIG. 1, a typical stage 10 of a conventional pipeline A/Dconverter includes a sample and hold circuit 12, an A/D conversioncircuit 14, a digital-to-analog (D/A) conversion circuit 16, a signalcombining circuit 18 and an output buffer amplifier 20, allinterconnected substantially as shown. By connecting N such stages 10serially together a pipeline A/D converter is formed. A clock signal 9synchronizes the operations of the sample and hold circuit 12, A/Dconverter 14 and D/A converter 16.

The analog residue signal 11 from the immediate upstream stage (i+1) issampled and held by the sample and hold circuit 12. This analog samplevoltage 13 is converted to a digital signal 15 (D_(i)) by the A/Dconverter 14. This digital signal 15 is provided as the binary bitinformation for that stage (i) and is also converted back to an analogsignal by the D/A converter 16. This analog signal 17 is summed with theoriginal analog sample voltage 13. The resulting sum voltage 19 is thenbuffered by the output amplifier 20 to provide the residue voltagesignal 21 for that stage 10. (A typical voltage gain for the outputamplifier 20 is two.)

Referring to FIG. 2A, the A/D converter 14 can be implemented with avoltage comparator 14a which compares the sample voltage 13 to areference voltage 13r. Referring to FIG. 2B, the D/A converter 16 can beimplemented with a latching multiplexor 16a which, in accordance withthe digital signal 15, selects between negative 15n and positive 15panalog voltages which are equal in magnitude for outputting as theanalog voltage 17 to be summed with the sample voltage 13.

Such analog processing stages for pipeline A/D converters (oftenreferred to as algorithmic A/D converters) have inherent imperfectionswhich negatively affect the linearity and, therefore, the accuracy ofsuch converters. For example, the number of linearity bits is determinedby the native matching of the passive components and is usually limitedto eight or ten bits. While it is possible to provide various forms oftrimming of the analog circuitry which have been proven to work up to 16bits of accuracy, such trimming procedures are very difficult andexpensive.

Accordingly, a commonly used alternative approach is that of digitalcalibration and correction. In such an approach, the errors attributedto the analog components are identified and compensated within thedigital domain. Examples of the techniques used in this approach can befound in the following references: S-H. Lee and B-S. Song,"Digital-Domain Calibration of Multistep Analog-to-Digital Converters,"IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, December 1992,pp. 1679-88; and A. N. Karanicolas, H-S. Lee and K. L. Bacrania, "A 15-b1-Msample/s Digitally Self-Calibrated Pipeline ADC," IEEE Journal ofSolid-State Circuits, Vol. 28, No. 12, December 1993, pp. 1207-15; thedisclosures of which are incorporated herein by reference.

A major concern about such digital calibration and correction algorithmsis that of the monotonicity of the transfer function. It has been shownthat any linear correction algorithm with multiple internalrepresentations of the same output code cannot guarantee themonotonicity of a converter transfer function. It has also been shownthat local discontinuities in the monotonicity can occur within theoutput code even after digital correction.

Whereas the presence of a few signal states where the monotonicity has alocal discontinuity may be acceptable in some applications, many closedloop control systems require virtually absolute monotonicity in order toavoid limit cycles. Further, local discontinuities in the monotonicitytend to be very difficult to detect by testing, can propagate toward themost significant bit and cannot be avoided by truncation since theirpositions are not known in advance.

As is well known, a common conventional digital calibration andcorrection technique involves the digital calibration of all of thetransitions within the residue signal transfer characteristics. Ananalog input signal equal to the transition voltage is applied at theinput of each stage and a decision is forced on both sides of suchtransition voltage. The resulting analog residue voltage is thenmeasured by the remaining stages within the pipeline (assumed to bealready calibrated or ideal). Based upon such measurements, correctioncoefficients for each transition are then stored in memory. Accordingly,each calibration step is equivalent to performing a digital shift of allof the residue segments along a common line (the ideal linear transfercharacteristic).

Initially such a calibration algorithm may appear to preserve overallmonotonicity since each step in the calibration procedure is monotonic.Indeed, this may be true if the analog calibration voltages areprecisely at the exact voltage transition points. However, due todifferent offsets in the individual voltage comparator circuits, theactual transition points are offset, or shifted, from their idealposition. These offsets in the transition point, when combined with theinherent gain errors, lead to a calibrated transition which is notprecisely equal to the actual transition gap. Therefore, the overalltransfer characteristic has discontinuities in its monotonicity.

Accordingly, it would be desirable to have a digital calibrationalgorithm which truly preserves overall monotonicity of its transfercharacteristic.

SUMMARY OF THE INVENTION

An apparatus and method for monotonic digital calibration of a pipelineA/D converter in accordance with the present invention forces an analoginput voltage at each calibrated stage which is precisely at the exactvoltage transition point for that particular stage. During calibrationof each stage, the actual input voltage comparator is used indetermining the analog input value for the corresponding transitioncalibration.

In accordance with one embodiment of the present invention, a method ofperforming a monotonic digital calibration of one or more stages of apipeline analog-to-digital (A/D) converter includes the steps of:receiving and converting in one of the multiple stages of a pipeline A/Dconverter an analog feedback signal to a digital signal which includesfirst and second digital signal states; converting the digital signal tothe analog feedback signal, such that the analog feedback signal ismaintained within a range of values for which the digital signal is inthe first and second digital signal states for approximately equalperiods of time; and generating, in accordance with the analog feedbacksignal in the one stage of the pipeline A/D converter, a residue signalwhich includes first and second signal levels which correspond to thefirst and second digital signal states, respectively.

In accordance with another embodiment of the present invention, apipeline analog-to-digital (A/D) converter with a monotonic digitalcalibration circuit includes a pipeline A/D converter and a feedbackdigital-to-analog (D/A) conversion circuit. Each of the multiple stagesof the pipeline A/D converter includes an A/D conversion circuit, aninput D/A conversion circuit and a signal combining circuit. The A/Dconversion circuit is configured to receive and convert an analogfeedback signal to a digital signal which includes first and seconddigital signal states. The input D/A conversion circuit is coupled tothe A/D conversion circuit and is configured to receive the digitalsignal and in accordance therewith provide an analog conversion signalwhich includes first and second conversion signal states whichcorrespond to the first and second digital signal states, respectively.The signal combining circuit is coupled to the A/D and input D/Aconversion circuits and is configured to receive and combine the analogfeedback signal and the analog conversion signal and in accordancetherewith provide a residue signal which includes first and secondsignal levels which correspond to the first and second digital signalstates, respectively. The feedback D/A conversion circuit is selectivelycoupled to one of the plurality of pipeline A/D converter stages and isconfigured to receive and convert the digital signal to the analogfeedback signal. The analog feedback signal is maintained within a rangeof values for which the digital signal is in the first and seconddigital signal states for approximately equal periods of time.

These and other features and advantages of the present invention will beunderstood upon consideration of the following detailed description ofthe invention and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of a conventional stage for apipeline A/D converter.

FIG. 2A is a functional block diagram of a conventional voltagecomparator used as an A/D converter.

FIG. 2B is a functional block diagram of a conventional multiplexor usedas a D/A converter.

FIG. 3 is a schematic diagram of a circuit in which an integratedfeedback voltage is used for performing a monotonic digital calibrationof one stage of a pipeline A/D converter using the corresponding inputA/D conversion circuit in accordance with one embodiment of the presentinvention.

FIG. 4 is a schematic diagram of a differential implementation of thecircuit of FIG. 3.

FIG. 5 is a functional block diagram of a pipeline A/D converter withcircuitry for performing monotonic digital calibration in accordancewith another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 3, a circuit 100 for performing monotonic digitalcalibration of one stage of a pipeline A/D converter in accordance withone embodiment of the present invention includes the voltage comparator14a of the stage 10 to be calibrated (FIG. 1) and a feedbackdigital-to-analog conversion circuit 102 in the form of a continuoustime voltage integration circuit interconnected by way of two signalrouting circuits such as switches SA, SD substantially as shown.

The switches SA/SD operate in unison such that when operating in thecalibration mode the digital output 15 from the voltage comparator 14ais fed back and converted to an analog signal 103, e.g., via integrationof the digital signal 15. The voltage integration circuit 102 integratesthe digital signal 15 based upon an input integration voltage reference101. The resulting feedback loop ensures that the average duty cycle forthe voltage comparator 14a output signal 15 is 50%. In turn, thisensures that the analog input voltage 13 of the comparator 14a isexactly at the voltage transition, or threshold, value. (The values forthe resistor R and capacitor C in the integration circuit 102 can beselected based upon the desired settling time and tolerable noise in theresulting analog voltage 103.)

Other forms of D/A conversion circuits can be used in place of thecontinuous time integration circuit 102. For example, other possibleimplementations include a switched-capacitor filter or a combination ofa digital filter with a low resolution D/A converter (e.g. an 8-bit D/Aconverter would cover a voltage range of -25 through +25 millivolts withsteps of 200 microvolts). One advantage of the filter and D/A convertercombination is that the analog input voltage can be held constant duringthe calibration cycle with increased noise immunity.

Referring to FIG. 4, a differential implementation 100d can be formed byusing a pair of input signal routing circuits SAp, SAn and adifferential conversion circuit 104, connected substantially as shown.The single-ended analog voltage 103 is converted to a differentialvoltage 105 (with positive 105p and negative 105n signal phases) basedupon an input voltage reference 103c. As with the single-endedconfiguration of FIG. 3, the switches SAp, SAn, SD operate in unison toform a feedback loop during calibration such that the single-endeddigital output signal 15 is converted to a differential analog voltage105 with a value which is maintained at the value of the transition, orthreshold, voltage of the comparator 14a.

Referring to FIG. 5, for calibrating each individual stage 10 of apipeline A/D converter, the feedback D/A converter 102 can be switched,or multiplexed, among the stages 10 individually using a switch matrix202. For example, for calibrating stage i 10(i) of the pipeline A/Dconverter switch SD(i) connects the digital output 15(i) of stage i tothe input of the feedback D/A converter 102 while switch SA(i) connectsthe output of the feedback D/A converter 102 to the input of stage i.The switches for the remaining downstream stages i-1, i-2, . . . , 1 arepositioned so as to maintain normal operation of such stages.Accordingly, the downstream stages i-1, i-2, . . . , 1 are used duringthe calibration process in accordance with well known conventionaltechniques. This process is repeated for each of the remaining upstreamstages n, n-1, . . . , i+1 following which the pipeline A/D converterhas been digitally calibrated for overall monotonicity.

Various other modifications and alterations in the structure and methodof operation of this invention will be apparent to those skilled in theart without departing from the scope and spirit of the invention.Although the invention has been described in connection with specificpreferred embodiments, it should be understood that the invention asclaimed should not be unduly limited to such specific embodiments. It isintended that the following claims define the scope of the presentinvention and that structures and methods within the scope of theseclaims and their equivalents be covered thereby.

What is claimed is:
 1. A method of performing a monotonic digitalcalibration of one or more stages of a pipeline analog-to-digital (A/D)converter, said method comprising the steps of:(a) receiving andconverting in one of a plurality of stages of a pipeline A/D converteran analog feedback signal to a digital signal which includes first andsecond digital signal states; (b) converting said digital signal to saidanalog feedback signal, wherein said analog feedback signal ismaintained within a range of values for which said digital signal is insaid first and second digital signal states for approximately equalperiods of time, and wherein said analog feedback signal varies withinsaid range of values in first and second continuously monotonicrelations which are between and opposite in polarity to precedingtransitions of said digital signal between said first and second digitalsignal states; and (c) generating, in accordance with said analogfeedback signal in said one of said plurality of stages of said pipelineA/D converter, a residue signal which includes first and second signallevels which correspond to said first and second digital signal states,respectively.
 2. The method of claim 1, wherein said step (a) comprisesreceiving and converting an analog feedback voltage to a digital voltagewith a voltage comparison circuit.
 3. The method of claim 1, whereinsaid step (b) comprises integrating a digital voltage and in accordancetherewith generating an analog integration voltage with a voltageintegration circuit.
 4. The method of claim 1, wherein said step (c)comprises generating said residue signal by summing said analog feedbacksignal with a summation signal which includes first and second summationsignal states which correspond to said first and second digital signalstates, respectively.
 5. The method of claim 1, further comprising thestep of repeating the steps of claim 1 successively for each remainingupstream one of said plurality of pipeline A/D converter stages.
 6. Themethod of claim 1, further comprising the step of measuring said firstand second residue signal levels with one or more remaining downstreamones of said plurality of stages of said pipeline A/D converter and inaccordance therewith generating A/D conversion calibration datacorresponding to said one of said plurality of stages of said pipelineA/D converter stage.
 7. The method of claim 6, further comprising thestep of repeating the steps of claims 1 and 6 successively for eachremaining upstream one of said plurality of pipeline A/D converterstages.
 8. An apparatus including a pipeline analog-to-digital (A/D)converter with a monotonic digital calibration circuit, comprising:apipeline A/D converter with a plurality of stages, wherein each one ofsaid plurality of pipeline A/D converter stages includesan A/Dconversion circuit configured to receive and convert an analog feedbacksignal to a digital signal which includes first and second digitalsignal states, an input digital-to-analog (D/A) conversion circuit,coupled to said A/D conversion circuit, configured to receive saiddigital signal and in accordance therewith provide an analog conversionsignal which includes first and second conversion signal states whichcorrespond to said first and second digital signal states, respectively,and a signal combining circuit, coupled to said A/D and input D/Aconversion circuits, configured to receive and combine said analogfeedback signal and said analog conversion signal and in accordancetherewith provide a residue signal which includes first and secondsignal levels which correspond to said first and second digital signalstates, respectively; and a feedback D/A conversion circuit, selectivelycoupled to one of said plurality of pipeline A/D converter stages,configured to receive and convert said digital signal to said analogfeedback signal, wherein said analog feedback signal is maintainedwithin a range of values for which said digital signal is in said firstand second digital signal states for approximately equal periods oftime, and wherein said analog feedback signal varies within said rangeof values in first and second continuously monotonic relations which arebetween and opposite in polarity to preceding transitions of saiddigital signal between said first and second digital signal states. 9.The apparatus of claim 8, wherein said A/D conversion circuit comprisesa voltage comparison circuit.
 10. The apparatus of claim 8, wherein saidinput D/A conversion circuit comprises a signal routing circuitconfigured to receive said digital signal and in accordance therewithroute one of a plurality of analog voltages to said signal combiningcircuit as said analog conversion signal.
 11. The apparatus of claim 8,wherein said signal combining circuit comprises a voltage summingcircuit.
 12. The apparatus of claim 8, wherein said feedback D/Aconversion circuit comprises a voltage integration circuit.
 13. Theapparatus of claim 8, further comprising a signal routing circuit,coupled between said feedback D/A conversion circuit and each one ofsaid plurality of pipeline A/D converter stages, configured toselectively couple said feedback D/A conversion circuit to individualones of said plurality of pipeline A/D converter stages.
 14. Theapparatus of claim 13, wherein said signal switching circuit comprises asignal multiplexor circuit configured to multiplex said digital signaland said analog feedback signal between said feedback D/A conversioncircuit and said individual ones of said plurality of pipeline A/Dconverter stages.